Scan based techniques offer an efficient alternative to achieve high fault coverage compared to the functional pattern based testing. As the design size increases and multi-core SoCs (system-on-chip) becomes essential to drive high speed applications, test data volume and test application time grow unwieldy even in the highly efficient and balanced scan based designs. Scan compression technique is so far, the best technique for test data volume as well as test time reduction during pattern execution of scan inserted designs. Scan compression architecture includes a decompressor for decompression of a data on an input side and a compressor for compression of the data on an output side. The decompressor takes scan inputs and expands them spatially into large number of scan chains internally. Each scan chain has a plurality of scan cells. The more the number of scan inputs to the decompressor, the better will be the expansion and larger will be the number of scan chains. Similarly on the output side of the scan compression architecture, the scan chains are compressed to a small number of scan outputs, also leading to the phenomenon of aliasing. Practically, if more number of scan outputs is available, the lesser will be aliasing and more robust will be the scan compression architecture. However, in case of a very low cost tester (VLCT), a maximum of 8 scan inputs and 8 scan outputs are supported. The maximum number of scan chains required to comprehend observation of scan chains on scan outputs, according to one known scan technique, would be 1024 (N*2(M-1), where N is number of scan inputs and M is number of scan outputs. Each scan chain has 128 scan cells and thus the total number of scan cells is 131072 (128*1024). If the number of scan input and scan output is 9, the number of scan chains would be 2304 and the number of scan cells in each scan chain would be approximately 57 (128×1024/256*9). Thus, when the number of scan inputs and scan outputs are increased from 8 to 9, the number of scan cells in each scan chain reduced by approximately 50%, thus reducing the time required for testing by a huge margin. However, VLCT does not support 9 scan inputs and 9 scan outputs.
In pin-limited devices, such as devices with 5 pins, the number of scan chains required would be 80 (5*2(5−1)). Thus, the number of scan cells required in each scan chain would be around 1638 (128*1024/80). As a result, the test timing would increase drastically. Also, to make VLCT compatible with pin-limited devices, a serializer approach is used. In this approach, at least two shift registers are used per scan input. Therefore to support the VLCT for the 5 pin device, a total of 10 shift registers are used at the input side. Further, as the data is shifted through two shift registers, a frequency of data shifting in scan cells is reduced by half, thus increasing the test timing. Also, since only 8 inputs are required, two of these scan inputs from the shift registers would be considered as don't care inputs. The shift registers is an additional overhead on the scan system. In a situation where optimal test timing is achieved at for example 9 pins, the serializer approach does not allow to support 9 pins for a 5 pin device. Thus, when A pins provide optimal test timing and the device is of B pins, the serializer approach does not support A/B, when A is not an integer multiple of B.